669 lines
22 KiB
ArmAsm
669 lines
22 KiB
ArmAsm
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
|
||
International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
|
||
Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/*******************************************************************************
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* mvDramIfBasicAsm.s
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*
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* DESCRIPTION:
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* Memory full detection and best timing configuration is done in
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* C code. C runtime environment requires a stack. This module API
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* initialize DRAM interface chip select 0 for basic functionality for
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* the use of stack.
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* The module API assumes DRAM information is stored in I2C EEPROM reside
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* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
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* internal data structure is assumed to be orgenzied in common DRAM
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* vendor SPD structure.
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* NOTE: DFCDL values are assumed to be already initialized prior to
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* this module API activity.
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*
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*
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* DEPENDENCIES:
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* None.
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*
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*******************************************************************************/
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/* includes */
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#define MV_ASMLANGUAGE
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#include "mvOsAsm.h"
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#include "mvSysHwConfig.h"
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#include "mvDramIfRegs.h"
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#include "mvDramIfConfig.h"
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#include "mvCpuIfRegs.h"
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#include "pex/mvPexRegs.h"
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#include "pci/mvPciRegs.h"
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#include "mvCtrlEnvSpec.h"
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#include "mvCtrlEnvAsm.h"
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#include "cpu/mvCpuArm.h"
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#include "mvCommon.h"
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/* defines */
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/* locals */
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.data
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.globl _mvDramIfConfig
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.text
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/*******************************************************************************
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* _mvDramIfConfig - Basic DRAM interface initialization.
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*
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* DESCRIPTION:
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* The function will initialize the following DRAM parameters using the
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* values prepared by mvDramIfDetect routine. Values are located
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* in predefined registers.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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_mvDramIfConfig:
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/* Save register on stack */
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cmp sp, #0
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beq no_stack_s
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save_on_stack:
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stmdb sp!, {r1, r2, r3, r4, r7, r11}
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no_stack_s:
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/* 1) Write to SDRAM coniguration register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
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str r4, [r1]
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/* 2) Write Dunit control low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
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str r4, [r1]
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/* 3) Write SDRAM address control register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
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str r4, [r1]
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/* 4) Write SDRAM bank 0 size register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0))
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str r4, [r1]
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/* 5) Write SDRAM open pages control register */
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ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
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ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
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str r4, [r1]
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/* 6) Write SDRAM timing Low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
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str r4, [r1]
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/* 7) Write SDRAM timing High register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
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str r4, [r1]
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/* 8) Write SDRAM mode register */
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/* The CPU must not attempt to change the SDRAM Mode register setting */
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/* prior to DRAM controller completion of the DRAM initialization */
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/* sequence. To guarantee this restriction, it is recommended that */
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/* the CPU sets the SDRAM Operation register to NOP command, performs */
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/* read polling until the register is back in Normal operation value, */
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/* and then sets SDRAM Mode register to it<69>s new value. */
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/* 8.1 write 'nop' to SDRAM operation */
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mov r4, #0x5 /* 'NOP' command */
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MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
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/* 8.2 poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll1:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll1
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/* 8.3 Now its safe to write new value to SDRAM Mode register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
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str r4, [r1]
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/* 8.4 Make the Dunit write the DRAM its new mode */
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mov r4, #0x3 /* Mode Register Set command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* 8.5 poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll2:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll2
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#ifndef DB_FPGA
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/* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
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MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG)
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tst r4, #SDRAM_DTYPE_DDR2
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beq _extModeODTEnd
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#endif /* DB_FPGA */
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/* 9) Write SDRAM Extended mode register This operation should be */
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/* done for each memory bank */
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/* write 'nop' to SDRAM operation */
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mov r4, #0x5 /* 'NOP' command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll3:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll3
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/* Now its safe to write new value to SDRAM Extended Mode register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
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str r4, [r1]
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/* Go over each of the Banks */
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ldr r3, =0 /* r3 = DRAM bank Num */
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extModeLoop:
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/* Set the SDRAM Operation Control to each of the DRAM banks */
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mov r2, r3 /* Do not swap the bank counter value */
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MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG)
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/* Make the Dunit write the DRAM its new mode */
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mov r4, #0x4 /* Extended Mode Register Set command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll4:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll4
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#ifndef DB_FPGA
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add r3, r3, #1
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cmp r3, #4 /* 4 = Number of banks */
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bne extModeLoop
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extModeEnd:
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/* Config DDR2 On Die Termination (ODT) registers */
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/* Write SDRAM DDR2 ODT control low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
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str r4, [r1]
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/* Write SDRAM DDR2 ODT control high register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
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str r4, [r1]
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/* Write SDRAM DDR2 Dunit ODT control register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
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str r4, [r1]
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#endif /* DB_FPGA */
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_extModeODTEnd:
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#ifndef DB_FPGA
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/* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
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/* Does Not Work for Address/Control and Data Pads. */
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/* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
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/* Read device ID */
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MV_CTRL_MODEL_GET_ASM(r3, r1);
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/* Read device revision */
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MV_CTRL_REV_GET_ASM(r2, r1);
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/* Continue if OrionN */
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ldr r1, =MV_5180_DEV_ID
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cmp r3, r1
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bne 1f
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b glMem2End
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1:
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/* Continue if Orion1 and device revision B1 */
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ldr r1, =MV_5181_DEV_ID
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cmp r3, r1
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bne 1f
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cmp r2, #MV_5181_B1_REV
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bge glMem2End
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b glMem2Start
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1:
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/* Orion NAS */
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ldr r1, =MV_5182_DEV_ID
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cmp r3, r1
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beq glMem2Start
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/* Orion NAS */
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ldr r1, =MV_5082_DEV_ID
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cmp r3, r1
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beq glMem2Start
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/* Orion Shark */
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ldr r1, =MV_8660_DEV_ID
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cmp r3, r1
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beq glMem2Start
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b glMem2End
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glMem2Start:
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/* DDR SDRAM Address/Control Pads Calibration */
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MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
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/* Set Bit [31] to make the register writable */
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orr r2, r3, #SDRAM_WR_EN
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MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
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bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
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bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
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bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
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bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
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/* Get the final N locked value of driving strength [22:17] */
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mov r1, r3
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mov r1, r1, LSL #9
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mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
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orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
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/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
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orr r3, r3, r1
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||
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MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||
|
||
|
||
/* DDR SDRAM Data Pads Calibration */
|
||
MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
|
||
/* Set Bit [31] to make the register writable */
|
||
orr r2, r3, #SDRAM_WR_EN
|
||
|
||
MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
|
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bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||
bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
|
||
bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
|
||
bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
|
||
|
||
/* Get the final N locked value of driving strength [22:17] */
|
||
mov r1, r3
|
||
mov r1, r1, LSL #9
|
||
mov r1, r1, LSR #26
|
||
orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
|
||
|
||
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
||
orr r3, r3, r1
|
||
|
||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
|
||
glMem2End:
|
||
|
||
|
||
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
|
||
/* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */
|
||
/* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */
|
||
|
||
/* Get SDRAM Config value */
|
||
MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG)
|
||
|
||
/* Get DIMM type */
|
||
tst r2, #SDRAM_DTYPE_DDR2
|
||
beq ddr1StrengthVal
|
||
|
||
ddr2StrengthVal:
|
||
ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||
ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
|
||
b setDrvStrength
|
||
ddr1StrengthVal:
|
||
ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||
ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
|
||
|
||
setDrvStrength:
|
||
/* DDR SDRAM Address/Control Pads Calibration */
|
||
MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||
|
||
orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
|
||
|
||
MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||
HTOLL(r3,r1)
|
||
|
||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||
bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||
orr r3, r4, r3 /* Set default value for DDR */
|
||
|
||
MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||
|
||
|
||
/* DDR SDRAM Data Pads Calibration */
|
||
MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
|
||
orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
|
||
|
||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
HTOLL(r3,r1)
|
||
|
||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||
bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||
orr r3, r2, r3 /* Set default value for DDR */
|
||
|
||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||
|
||
#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
|
||
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
|
||
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */
|
||
/* 88F5082, 88F5181L, 88F6082/L */
|
||
|
||
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
||
ldr r7, = _cpuARMDDRCLK
|
||
ldr r4, =_start
|
||
sub r7, r7, r4
|
||
add r7, r7, #CFG_MONITOR_BASE
|
||
|
||
/* Get the "sample on reset" register for the DDR frequancy */
|
||
MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET)
|
||
ldr r1, =MSAR_ARMDDRCLCK_MASK
|
||
and r1, r4, r1
|
||
#if 0 /* YOTAM TO BE FIX */
|
||
mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS
|
||
#endif
|
||
|
||
/* Read device ID */
|
||
MV_CTRL_MODEL_GET_ASM(r3, r2);
|
||
|
||
/* Continue if TC90 */
|
||
ldr r2, =MV_1281_DEV_ID
|
||
cmp r3, r2
|
||
beq armClkMsb
|
||
|
||
/* Continue if Orion2 */
|
||
ldr r2, =MV_5281_DEV_ID
|
||
cmp r3, r2
|
||
#if 0 /* YOTAM TO BE FIX */
|
||
bne 1f
|
||
#endif
|
||
|
||
armClkMsb:
|
||
#if 0 /* YOTAM TO BE FIX */
|
||
tst r4, #MSAR_ARMDDRCLCK_H_MASK
|
||
beq 1f
|
||
orr r1, r1, #BIT4
|
||
1:
|
||
ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
|
||
mul r1, r4, r1
|
||
add r7, r7, r1
|
||
add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
|
||
ldr r1, [r7]
|
||
#endif
|
||
|
||
/* Get SDRAM Config value */
|
||
MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG)
|
||
|
||
/* Get DIMM type */
|
||
tst r2, #SDRAM_DTYPE_DDR2
|
||
beq ddr1FtdllVal
|
||
|
||
ddr2FtdllVal:
|
||
ldr r2, =MV_5281_DEV_ID
|
||
cmp r3, r2
|
||
bne 2f
|
||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||
cmp r3, #MV_5281_D0_REV
|
||
beq orin2_d0_ddr2_ftdll_val
|
||
cmp r3, #MV_5281_D1_REV
|
||
beq orin2_d1_ddr2_ftdll_val
|
||
cmp r3, #MV_5281_D2_REV
|
||
beq orin2_d1_ddr2_ftdll_val
|
||
b ddr2_default_val
|
||
|
||
/* Set Orion 2 D1 ftdll values for DDR2 */
|
||
orin2_d1_ddr2_ftdll_val:
|
||
ldr r4, =FTDLL_DDR2_250MHZ_5281_D1
|
||
ldr r7, =_250MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_200MHZ_5281_D1
|
||
ldr r7, =_200MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
b ddr2_default_val
|
||
|
||
/* Set Orion 2 D0 ftdll values for DDR2 */
|
||
orin2_d0_ddr2_ftdll_val:
|
||
ldr r4, =FTDLL_DDR2_250MHZ_5281_D0
|
||
ldr r7, =_250MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_200MHZ_5281_D0
|
||
ldr r7, =_200MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
b ddr2_default_val
|
||
2:
|
||
ldr r2, =MV_5182_DEV_ID
|
||
cmp r3, r2
|
||
bne 3f
|
||
|
||
/* Set Orion nas ftdll values for DDR2 */
|
||
orin_nas_ftdll_val:
|
||
ldr r4, =FTDLL_DDR2_166MHZ_5182
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
|
||
/* default values for all other devices */
|
||
3:
|
||
ddr2_default_val:
|
||
ldr r4, =FTDLL_DDR2_250MHZ
|
||
ldr r7, =_250MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_200MHZ
|
||
ldr r7, =_200MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_166MHZ
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR2_133MHZ
|
||
ldr r7, =_133MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =0
|
||
b setFtdllReg
|
||
|
||
ddr1FtdllVal:
|
||
ldr r2, =MV_5281_DEV_ID
|
||
cmp r3, r2
|
||
bne 2f
|
||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||
cmp r3, #MV_5281_D0_REV
|
||
bge orin2_ddr1_ftdll_val
|
||
b ddr1_default_val
|
||
|
||
/* Set Orion 2 D0 and above ftdll values for DDR1 */
|
||
orin2_ddr1_ftdll_val:
|
||
ldr r4, =FTDLL_DDR1_200MHZ_5281_D0
|
||
ldr r7, =_200MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
ldr r4, =FTDLL_DDR1_166MHZ_5281_D0
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
b ddr1_default_val
|
||
2:
|
||
ldr r2, =MV_5181_DEV_ID
|
||
cmp r3, r2
|
||
bne 3f
|
||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||
cmp r3, #MV_5181_B1_REV
|
||
bge orin1_ddr1_ftdll_val
|
||
b ddr1_default_val
|
||
|
||
/* Set Orion 1 ftdll values for DDR1 */
|
||
orin1_ddr1_ftdll_val:
|
||
ldr r4, =FTDLL_DDR1_166MHZ_5181_B1
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
3:
|
||
ddr1_default_val:
|
||
ldr r4, =FTDLL_DDR1_133MHZ
|
||
ldr r7, =_133MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
|
||
ldr r4, =FTDLL_DDR1_166MHZ
|
||
ldr r7, =_166MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
|
||
ldr r4, =FTDLL_DDR1_200MHZ
|
||
ldr r7, =_200MHz
|
||
cmp r1, r7
|
||
beq setFtdllReg
|
||
|
||
ldr r4, =0
|
||
|
||
setFtdllReg:
|
||
|
||
MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
|
||
HTOLL(r4,r1)
|
||
bic r4, r4, #1
|
||
MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
|
||
|
||
#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */
|
||
#endif /* DB_FPGA */
|
||
|
||
restoreTmpRegs:
|
||
/* Restore the registers we used to save the DDR detect values */
|
||
|
||
ldr r4, =DRAM_BUF_REG0_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0)
|
||
|
||
ldr r4, =DRAM_BUF_REG1_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1)
|
||
|
||
ldr r4, =DRAM_BUF_REG2_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2)
|
||
|
||
ldr r4, =DRAM_BUF_REG3_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3)
|
||
|
||
ldr r4, =DRAM_BUF_REG4_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4)
|
||
|
||
ldr r4, =DRAM_BUF_REG5_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5)
|
||
|
||
ldr r4, =DRAM_BUF_REG6_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6)
|
||
|
||
ldr r4, =DRAM_BUF_REG7_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7)
|
||
|
||
ldr r4, =DRAM_BUF_REG8_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8)
|
||
|
||
ldr r4, =DRAM_BUF_REG9_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9)
|
||
|
||
ldr r4, =DRAM_BUF_REG10_DV
|
||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10)
|
||
|
||
|
||
/* Restore registers */
|
||
/* Save register on stack */
|
||
cmp sp, #0
|
||
beq no_stack_l
|
||
load_from_stack:
|
||
ldmia sp!, {r1, r2, r3, r4, r7, r11}
|
||
no_stack_l:
|
||
|
||
mov pc, lr
|
||
|