307 lines
14 KiB
C
307 lines
14 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvDramIfRegsh
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#define __INCmvDramIfRegsh
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/* DDR SDRAM Controller Address Decode Registers */
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/* SDRAM CSn Base Address Register (SCBAR) */
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#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8))
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#define SCBAR_BASE_OFFS 16
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#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS)
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#define SCBAR_BASE_ALIGNMENT 0x10000
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/* SDRAM CSn Size Register (SCSR) */
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#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8))
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#define SCSR_WIN_EN BIT0
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#define SCSR_SIZE_OFFS 16
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#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS)
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#define SCSR_SIZE_ALIGNMENT 0x10000
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/* configuration register */
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#define SDRAM_CONFIG_REG 0x1400
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#define SDRAM_REFRESH_OFFS 0
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#define SDRAM_REFRESH_MAX 0x3000
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#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS)
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#define SDRAM_DWIDTH_OFFS 14
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#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS)
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#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS)
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#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS)
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#define SDRAM_DTYPE_OFFS 16
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#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS)
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#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS)
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#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS)
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#define SDRAM_REGISTERED (1 << 17)
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#define SDRAM_PERR_OFFS 18
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#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS)
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#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS)
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#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS)
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#define SDRAM_DCFG_OFFS 20
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#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS)
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#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS)
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#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS)
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#define SDRAM_SRMODE (1 << 24)
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#define SDRAM_SRCLK_OFFS 25
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#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS)
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#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS)
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#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS)
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#define SDRAM_CATTH_OFFS 26
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#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS)
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/* dunit control register */
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#define SDRAM_DUNIT_CTRL_REG 0x1404
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#define SDRAM_CTRL_POS_OFFS 6
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#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS)
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#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS)
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#define SDRAM_CLK1DRV_OFFS 12
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#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS)
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#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS)
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#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS)
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#define SDRAM_LOCKEN_OFFS 18
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#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS)
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#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS)
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#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS)
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#define SDRAM_ST_BURST_DEL_OFFS 24
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#define SDRAM_ST_BURST_DEL_MAX 0xf
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#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX<<SDRAM_ST_BURST_DEL_OFFS)
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/* sdram timing control low register */
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#define SDRAM_TIMING_CTRL_LOW_REG 0x1408
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#define SDRAM_TRCD_OFFS 4
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#define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS)
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#define SDRAM_TRP_OFFS 8
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#define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS)
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#define SDRAM_TWR_OFFS 12
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#define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS)
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#define SDRAM_TWTR_OFFS 16
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#define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS)
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#define SDRAM_TRAS_OFFS 20
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#define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS)
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#define SDRAM_TRRD_OFFS 24
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#define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS)
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#define SDRAM_TRTP_OFFS 28
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#define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS)
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/* sdram timing control high register */
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#define SDRAM_TIMING_CTRL_HIGH_REG 0x140c
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#define SDRAM_TRFC_OFFS 0
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#define SDRAM_TRFC_MASK (0xF << SDRAM_TRFC_OFFS)
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#define SDRAM_TR2R_OFFS 4
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#define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS)
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#define SDRAM_TR2W_W2R_OFFS 6
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#define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS)
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#define SDRAM_TRFC_EXT_OFFS 8
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#define SDRAM_TRFC_EXT_MASK (0x1 << SDRAM_TRFC_EXT_OFFS)
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#define SDRAM_TW2W_OFFS 10
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#define SDRAM_TW2W_MASK (0x1 << SDRAM_TW2W_OFFS)
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/* address control register */
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#define SDRAM_ADDR_CTRL_REG 0x1410
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#define SDRAM_DSIZE_OFFS 4
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#define SDRAM_DSIZE_MASK (0x3 << SDRAM_DSIZE_OFFS)
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#define SDRAM_DSIZE_128Mb (0x0 << SDRAM_DSIZE_OFFS)
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#define SDRAM_DSIZE_256Mb (0x1 << SDRAM_DSIZE_OFFS)
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#define SDRAM_DSIZE_512Mb (0x2 << SDRAM_DSIZE_OFFS)
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/* SDRAM Open Pages Control registers */
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#define SDRAM_OPEN_PAGE_CTRL_REG 0x1414
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#define SDRAM_OPEN_PAGE_EN (0 << 0)
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#define SDRAM_OPEN_PAGE_DIS (1 << 0)
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/* sdram opertion register */
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#define SDRAM_OPERATION_REG 0x1418
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#define SDRAM_CMD_OFFS 0
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#define SDRAM_CMD_MASK (0x7 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS)
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#define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS)
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/* sdram mode register */
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#define SDRAM_MODE_REG 0x141c
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#define SDRAM_BURST_LEN_OFFS 0
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#define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS)
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#define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS)
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#define SDRAM_CL_OFFS 4
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#define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS)
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#define SDRAM_DDR1_CL_2 (0x2 << SDRAM_CL_OFFS)
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#define SDRAM_DDR1_CL_3 (0x3 << SDRAM_CL_OFFS)
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#define SDRAM_DDR1_CL_4 (0x4 << SDRAM_CL_OFFS)
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#define SDRAM_DDR1_CL_1_5 (0x5 << SDRAM_CL_OFFS)
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#define SDRAM_DDR1_CL_2_5 (0x6 << SDRAM_CL_OFFS)
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#define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS)
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#define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS)
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#define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS)
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#define SDRAM_TM_OFFS 7
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#define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS)
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#define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS)
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#define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS)
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#define SDRAM_DLL_OFFS 8
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#define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS)
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#define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS)
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#define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS)
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#define SDRAM_WR_OFFS 11
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#define SDRAM_WR_MAX 7
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#define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS)
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#define SDRAM_PD_OFFS 12
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#define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS)
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#define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS)
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#define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS)
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/* DDR SDRAM Extended Mode register (DSEMR) */
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#define SDRAM_EXTENDED_MODE_REG 0x1420
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#define DSEMR_DLL_ENABLE (1 << 0)
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#define DSEMR_DS_OFFS 1
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#define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS)
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#define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS)
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#define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS)
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#define DSEMR_RTT0_OFFS 2
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#define DSEMR_RTT1_OFFS 6
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#define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
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#define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
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#define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
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#define DSEMR_OCD_OFFS 7
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#define DSEMR_OCD_MASK (0x7 << DSEMR_OCD_OFFS)
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#define DSEMR_OCD_EXIT_CALIB (0 << DSEMR_OCD_OFFS)
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#define DSEMR_OCD_DRIVE1 (1 << DSEMR_OCD_OFFS)
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#define DSEMR_OCD_DRIVE0 (2 << DSEMR_OCD_OFFS)
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#define DSEMR_OCD_ADJUST_MODE (4 << DSEMR_OCD_OFFS)
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#define DSEMR_OCD_CALIB_DEFAULT (7 << DSEMR_OCD_OFFS)
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#define DSEMR_DQS_OFFS 10
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#define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS)
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#define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS)
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#define DSEMR_DQS_SINGLE_ENDED (0 << DSEMR_DQS_OFFS)
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#define DSEMR_RDQS_ENABLE (1 << 11)
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#define DSEMR_QOFF_OUTPUT_BUFF_EN (1 << 12)
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/* DDR SDRAM Operation Control Register */
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#define SDRAM_OPERATION_CTRL_REG 0x142c
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/* Dunit FTDLL Configuration Register */
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#define SDRAM_FTDLL_CONFIG_REG 0x1484
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/* Pads Calibration register */
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#define SDRAM_ADDR_CTRL_PADS_CAL_REG 0x14c0
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#define SDRAM_DATA_PADS_CAL_REG 0x14c4
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#define SDRAM_DRVN_OFFS 0
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#define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS)
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#define SDRAM_DRVP_OFFS 6
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#define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS)
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#define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12
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#define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
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#define SDRAM_TUNE_EN BIT16
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#define SDRAM_LOCK_OFFS 17
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#define SDRAM_LOCK_MAKS (0x1F << SDRAM_LOCK_OFFS)
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#define SDRAM_LOCKN_OFFS 17
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#define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS)
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#define SDRAM_LOCKP_OFFS 23
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#define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS)
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#define SDRAM_WR_EN (1 << 31)
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/* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */
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#define DDR2_SDRAM_ODT_CTRL_LOW_REG 0x1494
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#define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4)
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#define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum))
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#define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum))
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#define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4))
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#define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum))
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#define DSOCLR_ODT_WD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum))
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/* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */
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#define DDR2_SDRAM_ODT_CTRL_HIGH_REG 0x1498
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/* Optional control values to DSOCHR_ODT_EN macro */
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#define DDR2_ODT_CTRL_DUNIT 0
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#define DDR2_ODT_CTRL_NEVER 1
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#define DDR2_ODT_CTRL_ALWAYS 3
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#define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2)
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#define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum))
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#define DSOCHR_ODT_EN(odtNum, ctrl) ((1 << ctrl) << DSOCHR_ODT_RD_OFFS(odtNum))
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/* DDR2 Dunit ODT Control Register (DDOCR)*/
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#define DDR2_DUNIT_ODT_CONTROL_REG 0x149c
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#define DDOCR_ODT_RD_OFFS 0
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#define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS)
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#define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS)
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#define DDOCR_ODT_WR_OFFS 4
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#define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS)
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#define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS)
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#define DSOCR_ODT_EN_OFFS 8
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#define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS)
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#define DSOCR_ODT_EN(ctrl) ((1 << ctrl) << DSOCR_ODT_EN_OFFS)
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#define DSOCR_ODT_SEL_OFFS 10
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#define DSOCR_ODT_SEL_MASK (0x3 << DSOCR_ODT_SEL_OFFS)
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/* DDR SDRAM Initialization Control Register (DSICR) */
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#define DDR_SDRAM_INIT_CTRL_REG 0x1480
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#define DSICR_INIT_EN (1 << 0)
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#endif /* __INCmvDramIfRegsh */
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