819 lines
23 KiB
C
819 lines
23 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "eth-phy/mvEthPhy.h"
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#include "eth/gbe/mvEthRegs.h"
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#include "boardEnv/mvBoardEnvLib.h"
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static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable);
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/*******************************************************************************
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* mvEthPhyRegRead - Read from ethernet phy register.
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*
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* DESCRIPTION:
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* This function reads ethernet phy register.
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*
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* INPUT:
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* phyAddr - Phy address.
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* regOffs - Phy register offset.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* 16bit phy register value, or 0xffff on error
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data)
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{
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MV_U32 smiReg;
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volatile MV_U32 timeout;
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/* check parameters */
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if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK)
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{
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mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY device address %d\n",
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phyAddr);
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return MV_FAIL;
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}
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if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK)
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{
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mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY register offset %d\n",
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regOffs);
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return MV_FAIL;
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}
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timeout = ETH_PHY_TIMEOUT;
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/* wait till the SMI is not busy*/
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do
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{
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/* read smi register */
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smiReg = MV_REG_READ(ETH_PHY_SMI_REG);
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if (timeout-- == 0)
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{
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mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
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return MV_FAIL;
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}
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}while (smiReg & ETH_PHY_SMI_BUSY_MASK);
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/* fill the phy address and regiser offset and read opcode */
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smiReg = (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS )|
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ETH_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg);
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timeout=ETH_PHY_TIMEOUT;
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/*wait till readed value is ready */
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do
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{
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/* read smi register */
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smiReg=MV_REG_READ(ETH_PHY_SMI_REG);
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if (timeout-- == 0) {
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mvOsPrintf("mvEthPhyRegRead: SMI read-valid timeout\n");
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return MV_FAIL;
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}
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}while (!(smiReg & ETH_PHY_SMI_READ_VALID_MASK));
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/* Wait for the data to update in the SMI register */
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for(timeout = 0 ; timeout < ETH_PHY_TIMEOUT ; timeout++);
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*data = (MV_U16)( MV_REG_READ(ETH_PHY_SMI_REG) & ETH_PHY_SMI_DATA_MASK);
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return MV_OK;
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}
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/*******************************************************************************
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* mvEthPhyRegWrite - Write to ethernet phy register.
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*
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* DESCRIPTION:
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* This function write to ethernet phy register.
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*
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* INPUT:
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* phyAddr - Phy address.
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* regOffs - Phy register offset.
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* data - 16bit data.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_OK if write succeed, MV_BAD_PARAM on bad parameters , MV_ERROR on error .
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* MV_TIMEOUT on timeout
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data)
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{
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MV_U32 smiReg;
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volatile MV_U32 timeout;
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/* check parameters */
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if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK)
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{
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mvOsPrintf("mvEthPhyRegWrite: Err. Illegal phy address \n");
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return MV_BAD_PARAM;
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}
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if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK)
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{
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mvOsPrintf("mvEthPhyRegWrite: Err. Illegal register offset \n");
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return MV_BAD_PARAM;
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}
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timeout=ETH_PHY_TIMEOUT;
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/* wait till the SMI is not busy*/
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do
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{
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/* read smi register */
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smiReg=MV_REG_READ(ETH_PHY_SMI_REG);
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if (timeout-- == 0) {
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mvOsPrintf("mvEthPhyRegWrite: SMI busy timeout\n");
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return MV_TIMEOUT;
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}
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}while (smiReg & ETH_PHY_SMI_BUSY_MASK);
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/* fill the phy address and regiser offset and write opcode and data*/
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smiReg = (data << ETH_PHY_SMI_DATA_OFFS);
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smiReg |= (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS );
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smiReg &= ~ETH_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg);
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return MV_OK;
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}
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/*******************************************************************************
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* mvEthPhyReset - Reset ethernet Phy.
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*
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* DESCRIPTION:
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* This function resets a given ethernet Phy.
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*
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* INPUT:
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* phyAddr - Phy address.
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* timeout - in millisec
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*
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* OUTPUT:
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* None.
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*
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* RETURN: MV_OK - Success
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* MV_TIMEOUT - Timeout
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout)
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{
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MV_U16 phyRegData;
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/* Reset the PHY */
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if(mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
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return MV_FAIL;
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/* Set bit 15 to reset the PHY */
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phyRegData |= ETH_PHY_CTRL_RESET_MASK;
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mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
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/* Wait untill Auotonegotiation completed */
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while(timeout > 0)
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{
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mvOsSleep(100);
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timeout -= 100;
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if( mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK)
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return MV_FAIL;
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if(phyRegData & ETH_PHY_STATUS_AN_DONE_MASK)
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return MV_OK;
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}
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return MV_TIMEOUT;
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}
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/*******************************************************************************
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* mvEthPhyRestartAN - Restart ethernet Phy Auto-Negotiation.
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*
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* DESCRIPTION:
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* This function resets a given ethernet Phy.
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*
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* INPUT:
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* phyAddr - Phy address.
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* timeout - in millisec
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*
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* OUTPUT:
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* None.
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*
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* RETURN: MV_OK - Success
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* MV_TIMEOUT - Timeout
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout)
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{
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MV_U16 phyRegData;
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/* Reset the PHY */
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if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
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return MV_FAIL;
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/* Set bit 12 to Enable autonegotiation of the PHY */
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phyRegData |= ETH_PHY_CTRL_AN_ENABLE_MASK;
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/* Set bit 9 to Restart autonegotiation of the PHY */
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phyRegData |= ETH_PHY_CTRL_AN_RESTART_MASK;
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mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
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/* Wait untill Auotonegotiation completed */
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while(timeout > 0)
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{
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mvOsSleep(100);
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timeout -= 100;
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if( mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK)
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return MV_FAIL;
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if(phyRegData & ETH_PHY_STATUS_AN_DONE_MASK)
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return MV_OK;
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}
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return MV_TIMEOUT;
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}
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/*******************************************************************************
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* mvEthPhyCheckLink -
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*
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* DESCRIPTION:
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* check link in phy port
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*
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* INPUT:
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* phyAddr - Phy address.
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*
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* OUTPUT:
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* None.
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*
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* RETURN: MV_TRUE if link is up, MV_FALSE if down
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*
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*******************************************************************************/
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MV_BOOL mvEthPhyCheckLink( MV_U32 phyAddr )
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{
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MV_U16 val_st, val_ctrl, val_spec_st;
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/* read status reg */
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if( mvEthPhyRegRead( phyAddr, ETH_PHY_STATUS_REG, &val_st) != MV_OK )
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return MV_FALSE;
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/* read control reg */
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if( mvEthPhyRegRead( phyAddr, ETH_PHY_CTRL_REG, &val_ctrl) != MV_OK )
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return MV_FALSE;
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/* read special status reg */
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if( mvEthPhyRegRead( phyAddr, ETH_PHY_SPEC_STATUS_REG, &val_spec_st) != MV_OK )
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return MV_FALSE;
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/* Check for PHY exist */
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if((val_ctrl == ETH_PHY_SMI_DATA_MASK) && (val_st & ETH_PHY_SMI_DATA_MASK))
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return MV_FALSE;
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if(val_ctrl & ETH_PHY_CTRL_AN_ENABLE_MASK)
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{
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if(val_st & ETH_PHY_STATUS_AN_DONE_MASK)
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return MV_TRUE;
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else
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return MV_FALSE;
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}
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else
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{
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if(val_spec_st & ETH_PHY_SPEC_STATUS_LINK_MASK)
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return MV_TRUE;
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}
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return MV_FALSE;
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}
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/*******************************************************************************
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* mvEthPhyPrintStatus -
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*
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* DESCRIPTION:
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* print port Speed, Duplex, Auto-negotiation, Link.
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*
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* INPUT:
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* phyAddr - Phy address.
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*
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* OUTPUT:
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* None.
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*
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* RETURN: 16bit phy register value, or 0xffff on error
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyPrintStatus( MV_U32 phyAddr )
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{
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MV_U16 val;
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/* read control reg */
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if( mvEthPhyRegRead( phyAddr, ETH_PHY_CTRL_REG, &val) != MV_OK )
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return MV_ERROR;
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if( val & ETH_PHY_CTRL_AN_ENABLE_MASK )
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mvOsOutput( "Auto negotiation: Enabled\n" );
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else
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mvOsOutput( "Auto negotiation: Disabled\n" );
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/* read specific status reg */
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if( mvEthPhyRegRead( phyAddr, ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK )
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return MV_ERROR;
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switch (val & ETH_PHY_SPEC_STATUS_SPEED_MASK)
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{
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case ETH_PHY_SPEC_STATUS_SPEED_1000MBPS:
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mvOsOutput( "Speed: 1000 Mbps\n" );
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break;
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case ETH_PHY_SPEC_STATUS_SPEED_100MBPS:
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mvOsOutput( "Speed: 100 Mbps\n" );
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break;
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case ETH_PHY_SPEC_STATUS_SPEED_10MBPS:
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mvOsOutput( "Speed: 10 Mbps\n" );
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default:
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mvOsOutput( "Speed: Uknown\n" );
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break;
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}
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if( val & ETH_PHY_SPEC_STATUS_DUPLEX_MASK )
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mvOsOutput( "Duplex: Full\n" );
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else
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mvOsOutput( "Duplex: Half\n" );
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if( val & ETH_PHY_SPEC_STATUS_LINK_MASK )
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mvOsOutput("Link: up\n");
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else
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mvOsOutput("Link: down\n");
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return MV_OK;
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}
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/*******************************************************************************
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* mvEthE1111PhyBasicInit -
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*
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* DESCRIPTION:
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* Do a basic Init to the Phy , including reset
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*
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* INPUT:
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* ethPortNum - Ethernet port number
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*
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* OUTPUT:
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* None.
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*
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* RETURN: None
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*
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*******************************************************************************/
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MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum)
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{
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MV_U16 reg;
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MV_U32 regOff, data;
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/* Phy recv and tx delay */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®);
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reg |= BIT1 | BIT7;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg);
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/* Leds link and activity*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111);
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/* reset the phy */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
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reg |= BIT15;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
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if(mvBoardSpecInitGet(®Off, &data) == MV_TRUE)
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),regOff , data);
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}
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/*******************************************************************************
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* mvEthE1112PhyBasicInit -
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*
|
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* DESCRIPTION:
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* Do a basic Init to the Phy , including reset
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*
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* INPUT:
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* ethPortNum - Ethernet port number
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*
|
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* OUTPUT:
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* None.
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*
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* RETURN: None
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*
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*******************************************************************************/
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MV_VOID mvEthE1112PhyBasicInit(MV_U32 ethPortNum)
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{
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MV_U16 reg;
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/* Set phy address */
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/*MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));*/
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/* Implement PHY errata */
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,0x140);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,0x8140);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x103);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
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/* reset the phy */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
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reg |= BIT15;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
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}
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/*******************************************************************************
|
|
* mvEthE1116PhyBasicInit -
|
|
*
|
|
* DESCRIPTION:
|
|
* Do a basic Init to the Phy , including reset
|
|
*
|
|
* INPUT:
|
|
* ethPortNum - Ethernet port number
|
|
*
|
|
* OUTPUT:
|
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* None.
|
|
*
|
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* RETURN: None
|
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*
|
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*******************************************************************************/
|
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MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum)
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{
|
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MV_U16 reg;
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/* Set phy address */
|
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MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
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/* Leds link and activity*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
|
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reg &= ~0xf;
|
|
//Patch by QNAP:Fix OnBoard SATA LED and Ethernet LED
|
|
// reg |= 0x1;
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reg = 0x812;
|
|
/////////////////////////////////////////////////
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
|
|
|
|
/* Set RGMII delay */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,®);
|
|
reg |= (BIT5 | BIT4);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
|
|
|
|
/* reset the phy */
|
|
//Patch by QNAP:Fix OnBoard SATA LED and Ethernet LED
|
|
// mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
|
|
// reg |= BIT15;
|
|
// mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* mvEthE1011PhyBasicInit -
|
|
*
|
|
* DESCRIPTION:
|
|
* Do a basic Init to the Phy , including reset
|
|
*
|
|
* INPUT:
|
|
* ethPortNum - Ethernet port number
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN: None
|
|
*
|
|
*******************************************************************************/
|
|
MV_VOID mvEthE1011PhyBasicInit(MV_U32 ethPortNum)
|
|
{
|
|
MV_U16 reg;
|
|
|
|
/* Phy recv and tx delay */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®);
|
|
reg &= ~(BIT1 | BIT7);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg);
|
|
|
|
/* Leds link and activity*/
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111);
|
|
|
|
/* reset the phy */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0, ®);
|
|
reg |= BIT15;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
|
|
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* mvEthE1112PhyPowerDown -
|
|
*
|
|
* DESCRIPTION:
|
|
* Power down the Phy , including reset
|
|
*
|
|
* INPUT:
|
|
* ethPortNum - Ethernet port number
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN: None
|
|
*
|
|
*******************************************************************************/
|
|
MV_VOID mvEthE1112PhyPowerDown(MV_U32 ethPortNum)
|
|
{
|
|
mvEthPhyPower(ethPortNum, MV_FALSE);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* mvEthE1112PhyPowerUp -
|
|
*
|
|
* DESCRIPTION:
|
|
* Power up the Phy , including reset
|
|
*
|
|
* INPUT:
|
|
* ethPortNum - Ethernet port number
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN: None
|
|
*
|
|
*******************************************************************************/
|
|
MV_VOID mvEthE1112PhyPowerUp(MV_U32 ethPortNum)
|
|
{
|
|
mvEthPhyPower(ethPortNum, MV_TRUE);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* mvEthPhyPower -
|
|
*
|
|
* DESCRIPTION:
|
|
* Do a basic power down/up to the Phy , including reset
|
|
*
|
|
* INPUT:
|
|
* ethPortNum - Ethernet port number
|
|
* enable - MV_TRUE - power up
|
|
* MV_FALSE - power down
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN: None
|
|
*
|
|
*******************************************************************************/
|
|
static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable)
|
|
{
|
|
MV_U16 reg;
|
|
if (enable == MV_FALSE)
|
|
{
|
|
/* Power down command */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
|
|
reg |= BIT3;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to disable the SERDES */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power off LED's */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x88);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
|
|
reg |= ETH_PHY_CTRL_RESET_BIT;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
|
|
reg |= ETH_PHY_CTRL_POWER_DOWN_BIT;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power down the PHY */
|
|
}
|
|
else
|
|
{
|
|
/* Power up command */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
|
|
reg &= ~BIT3;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to enable the SERDES */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power on LED's */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x03);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
|
|
reg |= ETH_PHY_CTRL_RESET_BIT;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
|
|
reg &= ~ETH_PHY_CTRL_POWER_DOWN_BIT;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power up the PHY */
|
|
}
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* INPUT:
|
|
* phyAddr - Phy address.
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* None.
|
|
*
|
|
*******************************************************************************/
|
|
MV_VOID mvEth1145PhyBasicInit(MV_U32 port)
|
|
{
|
|
MV_U16 value;
|
|
|
|
/* Set phy address for each port */
|
|
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), mvBoardPhyAddrGet(port));
|
|
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x18, ETH_PHY_LED_ACT_LNK_DV);
|
|
mvOsDelay(10);
|
|
|
|
/* Add delay to RGMII Tx and Rx */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x14, &value);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x14,(value | BIT1 | BIT7));
|
|
mvOsDelay(10);
|
|
#if 0 /* Fix by yotam */
|
|
if (boardId != RD_78XX0_AMC_ID &&
|
|
boardId != RD_78XX0_H3C_ID) {
|
|
/* Set port 2 - Phy addr 9 to RGMII */
|
|
if (port == 2)
|
|
{
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x808b);
|
|
mvOsDelay(10);
|
|
}
|
|
|
|
/* Set port 1 - Phy addr a to SGMII */
|
|
if (port == 1)
|
|
{
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x8084);
|
|
mvOsDelay(10);
|
|
|
|
/* Reset Phy */
|
|
mvEthPhyRegRead( mvBoardPhyAddrGet(port), 0x00, &value);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
|
|
mvOsDelay(10);
|
|
#if defined(SGMII_OUTBAND_AN)
|
|
/* Set port 1 - Phy addr A Page 1 */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x1);
|
|
mvOsDelay(10);
|
|
|
|
/* Set port 1 - Phy addr A disable A.N. */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x140);
|
|
mvOsDelay(10);
|
|
|
|
/* Set port 1 - Phy addr A reset */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x8140);
|
|
mvOsDelay(10);
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x0);
|
|
mvOsDelay(10);
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Set Phy TPVL to 0 */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x10, 0x60);
|
|
mvOsDelay(10);
|
|
|
|
/* Reset Phy */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x00, &value);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
|
|
mvOsDelay(10);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* mvEthSgmiiToCopperPhyInit - Initialize Test board 1112 Phy
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* INPUT:
|
|
* phyAddr - Phy address.
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* None.
|
|
*
|
|
*******************************************************************************/
|
|
MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 port)
|
|
{
|
|
MV_U16 value;
|
|
MV_U16 phyAddr = 0xC;
|
|
|
|
/* Port 0 phyAdd c */
|
|
/* Port 1 phyAdd d */
|
|
mvEthPhyRegWrite(phyAddr + port,22,3);
|
|
mvEthPhyRegWrite(phyAddr + port,16,0x103);
|
|
mvEthPhyRegWrite(phyAddr + port,22,0);
|
|
|
|
/* reset the phy */
|
|
mvEthPhyRegRead(phyAddr + port,0,&value);
|
|
value |= BIT15;
|
|
mvEthPhyRegWrite(phyAddr + port,0,value);
|
|
}
|
|
|
|
|
|
MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
|
|
{
|
|
MV_U16 value;
|
|
MV_U16 phyAddr = mvBoardPhyAddrGet(port);
|
|
|
|
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);
|
|
|
|
/* Change page select to 2 */
|
|
value = 2;
|
|
mvEthPhyRegWrite(phyAddr, 22, value);
|
|
mvOsDelay(10);
|
|
|
|
/* Set RGMII rx delay */
|
|
mvEthPhyRegRead(phyAddr, 21, &value);
|
|
value |= BIT5;
|
|
mvEthPhyRegWrite(phyAddr, 21, value);
|
|
mvOsDelay(10);
|
|
|
|
/* Change page select to 0 */
|
|
value = 0;
|
|
mvEthPhyRegWrite(phyAddr, 22, value);
|
|
mvOsDelay(10);
|
|
|
|
/* reset the phy */
|
|
mvEthPhyRegRead(phyAddr, 0, &value);
|
|
value |= BIT15;
|
|
mvEthPhyRegWrite(phyAddr, 0, value);
|
|
mvOsDelay(10);
|
|
}
|
|
|