252 lines
6.5 KiB
C
252 lines
6.5 KiB
C
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#if defined(CONFIG_MPC5200_DDR)
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#include "mt46v16m16-75.h"
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#else
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#include "mt48lc16m32s2-75.h"
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#endif
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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#if defined(CONFIG_MPC5200)
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
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/* find RAM size using SDRAM CS1 only */
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if (!dramsize)
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sdram_start(0);
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test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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if (!dramsize) {
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sdram_start(1);
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test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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}
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20)) {
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dramsize2 = 0;
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}
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
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| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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}
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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} else {
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dramsize2 = 0;
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}
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#endif /* CFG_RAMBOOT */
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return dramsize + dramsize2;
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}
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#elif defined(CONFIG_MGT5100)
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup and enable SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
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*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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/* address select register */
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*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
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__asm__ volatile ("sync");
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/* find RAM size */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* set SDRAM end address according to size */
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*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
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#else /* CFG_RAMBOOT */
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/* Retrieve amount of SDRAM available */
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dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
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#endif /* CFG_RAMBOOT */
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return dramsize;
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}
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#else
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#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
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#endif
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int checkboard (void)
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{
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puts ("Board: CANMB\n");
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return 0;
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}
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int board_early_init_r (void)
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{
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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*(vu_long *)MPC5XXX_BOOTCS_START =
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*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
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*(vu_long *)MPC5XXX_BOOTCS_STOP =
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*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
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return 0;
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}
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