485 lines
16 KiB
C
485 lines
16 KiB
C
/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
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/******************************************************************************
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (c) Copyright 2002 Xilinx Inc.
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* All rights reserved.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic_l.c
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*
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* This file contains low-level driver functions that can be used to access the
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* device. The user should refer to the hardware device specification for more
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* details of the device operation.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- ------- -----------------------------------------------
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* 1.01b jhl 5/13/02 First release
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* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
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* interrupt status mask was not being done in the loop such
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* that a read would sometimes fail on the last byte because
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* the transmit error which should have been ignored was
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* being used. This would leave an extra byte in the FIFO
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* and the bus throttled such that the next operation would
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* also fail. Also updated the receive function to not
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* disable the device after the last byte until after the
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* bus transitions to not busy which is more consistent
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* with the expected behavior.
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* 1.01c ecm 12/05/02 new rev
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* </pre>
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*
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****************************************************************************/
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/***************************** Include Files *******************************/
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#include "xbasic_types.h"
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#include "xio.h"
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#include "xipif_v1_23_b.h"
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#include "xiic_l.h"
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/************************** Constant Definitions ***************************/
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/**************************** Type Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *******************/
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/******************************************************************************
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*
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* This macro clears the specified interrupt in the IPIF interrupt status
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* register. It is non-destructive in that the register is read and only the
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* interrupt specified is cleared. Clearing an interrupt acknowledges it.
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*
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* @param BaseAddress contains the IPIF registers base address.
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*
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* @param InterruptMask contains the interrupts to be disabled
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*
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* @return
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*
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* None.
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*
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* @note
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*
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* Signature: void XIic_mClearIisr(u32 BaseAddress,
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* u32 InterruptMask);
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*
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******************************************************************************/
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#define XIic_mClearIisr(BaseAddress, InterruptMask) \
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XIIF_V123B_WRITE_IISR((BaseAddress), \
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XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
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/******************************************************************************
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*
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* This macro sends the address for a 7 bit address during both read and write
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* operations. It takes care of the details to format the address correctly.
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* This macro is designed to be called internally to the drivers.
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*
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* @param SlaveAddress contains the address of the slave to send to.
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*
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* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
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*
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* @return
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*
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* None.
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*
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* @note
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*
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* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
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*
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******************************************************************************/
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#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation) \
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{ \
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u8 LocalAddr = (u8)(SlaveAddress << 1); \
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LocalAddr = (LocalAddr & 0xFE) | (Operation); \
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XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr); \
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}
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/************************** Function Prototypes ****************************/
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static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
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unsigned ByteCount);
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static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
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unsigned ByteCount);
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/************************** Variable Definitions **************************/
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/****************************************************************************/
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/**
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* Receive data as a master on the IIC bus. This function receives the data
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* using polled I/O and blocks until the data has been received. It only
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* supports 7 bit addressing and non-repeated start modes of operation. The
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* user is responsible for ensuring the bus is not busy if multiple masters
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* are present on the bus.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param Address contains the 7 bit IIC address of the device to send the
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* specified data to.
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* @param BufferPtr points to the data to be sent.
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* @param ByteCount is the number of bytes to be sent.
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*
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* @return
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*
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* The number of bytes received.
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*
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* @note
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*
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* None
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*
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******************************************************************************/
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unsigned XIic_Recv (u32 BaseAddress, u8 Address,
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u8 * BufferPtr, unsigned ByteCount)
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{
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u8 CntlReg;
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unsigned RemainingByteCount;
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/* Tx error is enabled incase the address (7 or 10) has no device to answer
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* with Ack. When only one byte of data, must set NO ACK before address goes
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* out therefore Tx error must not be enabled as it will go off immediately
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* and the Rx full interrupt will be checked. If full, then the one byte
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* was received and the Tx error will be disabled without sending an error
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* callback msg.
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*/
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XIic_mClearIisr (BaseAddress,
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XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK);
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/* Set receive FIFO occupancy depth for 1 byte (zero based)
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*/
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XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
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/* 7 bit slave address, send the address for a read operation
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* and set the state to indicate the address has been sent
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*/
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XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
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/* MSMS gets set after putting data in FIFO. Start the master receive
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* operation by setting CR Bits MSMS to Master, if the buffer is only one
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* byte, then it should not be acknowledged to indicate the end of data
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*/
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CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
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if (ByteCount == 1) {
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CntlReg |= XIIC_CR_NO_ACK_MASK;
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}
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/* Write out the control register to start receiving data and call the
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* function to receive each byte into the buffer
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
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/* Clear the latched interrupt status for the bus not busy bit which must
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* be done while the bus is busy
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*/
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XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
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/* Try to receive the data from the IIC bus */
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RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
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/*
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* The receive is complete, disable the IIC device and return the number of
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* bytes that was received
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
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/* Return the number of bytes that was received */
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return ByteCount - RemainingByteCount;
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}
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/******************************************************************************
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*
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* Receive the specified data from the device that has been previously addressed
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* on the IIC bus. This function assumes that the 7 bit address has been sent
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* and it should wait for the transmit of the address to complete.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param BufferPtr points to the buffer to hold the data that is received.
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* @param ByteCount is the number of bytes to be received.
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*
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* @return
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*
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* The number of bytes remaining to be received.
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*
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* @note
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*
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* This function does not take advantage of the receive FIFO because it is
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* designed for minimal code space and complexity. It contains loops that
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* that could cause the function not to return if the hardware is not working.
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*
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* This function assumes that the calling function will disable the IIC device
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* after this function returns.
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*
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******************************************************************************/
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static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
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{
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u8 CntlReg;
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u32 IntrStatusMask;
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u32 IntrStatus;
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/* Attempt to receive the specified number of bytes on the IIC bus */
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while (ByteCount > 0) {
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/* Setup the mask to use for checking errors because when receiving one
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* byte OR the last byte of a multibyte message an error naturally
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* occurs when the no ack is done to tell the slave the last byte
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*/
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if (ByteCount == 1) {
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IntrStatusMask =
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XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
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} else {
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IntrStatusMask =
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XIIC_INTR_ARB_LOST_MASK |
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XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
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}
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/* Wait for the previous transmit and the 1st receive to complete
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* by checking the interrupt status register of the IPIF
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*/
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while (1) {
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IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
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if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
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break;
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}
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/* Check the transmit error after the receive full because when
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* sending only one byte transmit error will occur because of the
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* no ack to indicate the end of the data
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*/
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if (IntrStatus & IntrStatusMask) {
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return ByteCount;
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}
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}
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CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
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/* Special conditions exist for the last two bytes so check for them
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* Note that the control register must be setup for these conditions
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* before the data byte which was already received is read from the
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* receive FIFO (while the bus is throttled
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*/
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if (ByteCount == 1) {
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/* For the last data byte, it has already been read and no ack
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* has been done, so clear MSMS while leaving the device enabled
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* so it can get off the IIC bus appropriately with a stop.
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
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XIIC_CR_ENABLE_DEVICE_MASK);
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}
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/* Before the last byte is received, set NOACK to tell the slave IIC
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* device that it is the end, this must be done before reading the byte
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* from the FIFO
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*/
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if (ByteCount == 2) {
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/* Write control reg with NO ACK allowing last byte to
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* have the No ack set to indicate to slave last byte read.
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
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CntlReg | XIIC_CR_NO_ACK_MASK);
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}
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/* Read in data from the FIFO and unthrottle the bus such that the
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* next byte is read from the IIC bus
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*/
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*BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
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/* Clear the latched interrupt status so that it will be updated with
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* the new state when it changes, this must be done after the receive
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* register is read
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*/
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XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
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XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK);
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ByteCount--;
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}
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/* Wait for the bus to transition to not busy before returning, the IIC
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* device cannot be disabled until this occurs. It should transition as
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* the MSMS bit of the control register was cleared before the last byte
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* was read from the FIFO.
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*/
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while (1) {
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if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
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break;
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}
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}
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return ByteCount;
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}
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/****************************************************************************/
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/**
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* Send data as a master on the IIC bus. This function sends the data
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* using polled I/O and blocks until the data has been sent. It only supports
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* 7 bit addressing and non-repeated start modes of operation. The user is
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* responsible for ensuring the bus is not busy if multiple masters are present
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* on the bus.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param Address contains the 7 bit IIC address of the device to send the
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* specified data to.
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* @param BufferPtr points to the data to be sent.
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* @param ByteCount is the number of bytes to be sent.
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*
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* @return
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*
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* The number of bytes sent.
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*
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* @note
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*
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* None
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*
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******************************************************************************/
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unsigned XIic_Send (u32 BaseAddress, u8 Address,
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u8 * BufferPtr, unsigned ByteCount)
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{
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unsigned RemainingByteCount;
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/* Put the address into the FIFO to be sent and indicate that the operation
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* to be performed on the bus is a write operation
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*/
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XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
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/* Clear the latched interrupt status so that it will be updated with the
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* new state when it changes, this must be done after the address is put
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* in the FIFO
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*/
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XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
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XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
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/* MSMS must be set after putting data into transmit FIFO, indicate the
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* direction is transmit, this device is master and enable the IIC device
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
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XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
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XIIC_CR_ENABLE_DEVICE_MASK);
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/* Clear the latched interrupt
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* status for the bus not busy bit which must be done while the bus is busy
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*/
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XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
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/* Send the specified data to the device on the IIC bus specified by the
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* the address
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*/
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RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
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/*
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* The send is complete, disable the IIC device and return the number of
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* bytes that was sent
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
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return ByteCount - RemainingByteCount;
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}
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/******************************************************************************
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*
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* Send the specified buffer to the device that has been previously addressed
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* on the IIC bus. This function assumes that the 7 bit address has been sent
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* and it should wait for the transmit of the address to complete.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param BufferPtr points to the data to be sent.
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* @param ByteCount is the number of bytes to be sent.
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*
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* @return
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*
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* The number of bytes remaining to be sent.
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*
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* @note
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*
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* This function does not take advantage of the transmit FIFO because it is
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* designed for minimal code space and complexity. It contains loops that
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* that could cause the function not to return if the hardware is not working.
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*
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******************************************************************************/
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static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
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{
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u32 IntrStatus;
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/* Send the specified number of bytes in the specified buffer by polling
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* the device registers and blocking until complete
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*/
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while (ByteCount > 0) {
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/* Wait for the transmit to be empty before sending any more data
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* by polling the interrupt status register
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*/
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while (1) {
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IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
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if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK |
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XIIC_INTR_BNB_MASK)) {
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return ByteCount;
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}
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if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
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break;
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}
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}
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/* If there is more than one byte to send then put the next byte to send
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* into the transmit FIFO
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*/
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if (ByteCount > 1) {
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XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
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*BufferPtr++);
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} else {
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/* Set the stop condition before sending the last byte of data so that
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* the stop condition will be generated immediately following the data
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* This is done by clearing the MSMS bit in the control register.
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*/
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XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
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XIIC_CR_ENABLE_DEVICE_MASK |
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XIIC_CR_DIR_IS_TX_MASK);
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/* Put the last byte to send in the transmit FIFO */
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XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
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*BufferPtr++);
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}
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/* Clear the latched interrupt status register and this must be done after
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* the transmit FIFO has been written to or it won't clear
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*/
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XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
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/* Update the byte count to reflect the byte sent and clear the latched
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* interrupt status so it will be updated for the new state
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*/
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ByteCount--;
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}
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/* Wait for the bus to transition to not busy before returning, the IIC
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* device cannot be disabled until this occurs.
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* Note that this is different from a receive operation because the stop
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* condition causes the bus to go not busy.
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*/
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while (1) {
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if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
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break;
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}
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}
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return ByteCount;
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}
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