179 lines
4.2 KiB
C
179 lines
4.2 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#ifdef CONFIG_SDRAM_BANK0
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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struct sdram_conf_s {
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unsigned long size;
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unsigned long reg;
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};
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typedef struct sdram_conf_s sdram_conf_t;
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#ifndef CFG_SDRAM_TABLE
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sdram_conf_t mb0cf[] = {
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{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
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{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
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{(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
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{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
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{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
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};
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#else
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sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
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#endif
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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#ifndef CONFIG_440
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/*
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* Autodetect onboard SDRAM on 405 platforms
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*/
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void sdram_init(void)
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{
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ulong sdtr1;
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ulong rtr;
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int i;
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/*
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* Support for 100MHz and 133MHz SDRAM
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*/
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if (get_bus_freq(0) > 100000000) {
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/*
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* 133 MHz SDRAM
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*/
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sdtr1 = 0x01074015;
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rtr = 0x07f00000;
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} else {
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/*
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* default: 100 MHz SDRAM
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*/
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sdtr1 = 0x0086400d;
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rtr = 0x05f00000;
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}
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for (i=0; i<N_MB0CF; i++) {
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0.
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*/
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mtsdram0(mem_mb0cf, mb0cf[i].reg);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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/*
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* OK, size detected -> all done
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*/
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return;
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}
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}
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}
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#else /* CONFIG_440 */
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/*
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* Autodetect onboard DDR SDRAM on 440 platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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long int initdram(int board_type)
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{
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int i;
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for (i=0; i<N_MB0CF; i++) {
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/*
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* Disable memory controller.
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*/
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mtsdram(mem_cfg0, 0x00000000);
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/*
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* Setup some default
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*/
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(mem_b0cr, mb0cf[i].reg);
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mtsdram(mem_tr0, 0x41094012);
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mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
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mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20<EFBFBD>s @ 133MHz PLB*/
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
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udelay(400); /* Delay 200 usecs (min) */
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/*
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* Enable the controller, then wait for DCEN to complete
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*/
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mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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/*
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* OK, size detected -> all done
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*/
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return mb0cf[i].size;
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}
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}
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return 0; /* nothing found ! */
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}
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#endif /* CONFIG_440 */
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#endif /* CONFIG_SDRAM_BANK0 */
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