245 lines
7.5 KiB
C
245 lines
7.5 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuration settings for the PLEB 2 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
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#define CONFIG_PLEB2 1 /* on an PLEB2 Board */
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#undef CONFIG_LCD
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#undef CONFIG_MMC
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#define BOARD_LATE_INIT 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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/* None - PLEB 2 doesn't have any of this.
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#define CONFIG_DRIVER_LAN91C96
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#define CONFIG_LAN91C96_BASE 0x0C000000 */
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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#define CONFIG_SERVERIP 192.168.0.250
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#define CONFIG_BOOTCOMMAND "bootm 40000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER 1
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#endif
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */
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/* Not entirely sure about this - DS/CHC */
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#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
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#define CFG_DRAM_BASE PHYS_SDRAM_1
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#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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/*
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* GPIO settings
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*/
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#define CFG_GPSR0_VAL 0x00000000 /* Don't set anything */
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#define CFG_GPSR1_VAL 0x00000080
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#define CFG_GPSR2_VAL 0x00000000
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#define CFG_GPCR0_VAL 0x00000000 /* Don't clear anything */
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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#define CFG_GPDR0_VAL 0x00000000
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#define CFG_GPDR1_VAL 0x000007C3
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#define CFG_GPDR2_VAL 0x00000000
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/* Edge detect registers (these are set by the kernel) */
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#define CFG_GRER0_VAL 0x00000000
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#define CFG_GRER1_VAL 0x00000000
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#define CFG_GRER2_VAL 0x00000000
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#define CFG_GFER0_VAL 0x00000000
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#define CFG_GFER1_VAL 0x00000000
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#define CFG_GFER2_VAL 0x00000000
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#define CFG_GAFR0_L_VAL 0x00000000
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#define CFG_GAFR0_U_VAL 0x00000000
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#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
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#define CFG_GAFR1_U_VAL 0x00000000
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#define CFG_GAFR2_L_VAL 0x00000000
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#define CFG_GAFR2_U_VAL 0x00000000
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#define CFG_PSSR_VAL 0x20
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#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
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#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
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#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */
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#define CFG_MSC1_VAL 0x00000000
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#define CFG_MSC2_VAL 0x00000000
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#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM.
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tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
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#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual */
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/* bits set in lowlevel_init.S */
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#define CFG_MDMRS_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000000 /* Hangover from Lubbock.
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Needs calculating. (DS/CHC) */
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#define CFG_MCMEM0_VAL 0x00010504
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#define CFG_MCMEM1_VAL 0x00010504
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#define CFG_MCATT0_VAL 0x00010504
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#define CFG_MCATT1_VAL 0x00010504
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#define CFG_MCIO0_VAL 0x00004715
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#define CFG_MCIO1_VAL 0x00004715
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/*
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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/* FIXME */
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#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
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/* Flash protection */
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#define CFG_FLASH_PROTECTION 1
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/* FIXME */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
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#define CFG_ENV_SECT_SIZE 0x20000
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/* Option added to get around byte ordering issues in the flash driver */
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#define CFG_LITTLE_ENDIAN 1
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#endif /* __CONFIG_H */
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