2024-01-07 23:57:24 +01:00
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/******************************************************************************
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*
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* Name: skgesirq.h
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2024-01-07 23:58:22 +01:00
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* Project: Gigabit Ethernet Adapters, Common Modules
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* Version: $Revision: 1.1.1.1 $
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2024-01-08 00:07:02 +01:00
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* Date: $Date: 2008/12/15 11:39:21 $
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2024-01-07 23:58:22 +01:00
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* Purpose: Gigabit Ethernet special IRQ functions
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2024-01-07 23:57:24 +01:00
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*
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******************************************************************************/
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/******************************************************************************
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*
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2024-01-07 23:58:22 +01:00
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* LICENSE:
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* (C)Copyright 1998-2002 SysKonnect.
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* (C)Copyright 2002-2005 Marvell.
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2024-01-07 23:57:24 +01:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* The information in this file is provided "AS IS" without warranty.
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2024-01-07 23:58:22 +01:00
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* /LICENSE
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2024-01-07 23:57:24 +01:00
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*
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******************************************************************************/
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#ifndef _INC_SKGESIRQ_H_
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#define _INC_SKGESIRQ_H_
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2024-01-07 23:58:22 +01:00
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/* Define return codes of SkGePortCheckUp and CheckShort */
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#define SK_HW_PS_NONE 0 /* No action needed */
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#define SK_HW_PS_RESTART 1 /* Restart needed */
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#define SK_HW_PS_LINK 2 /* Link Up actions needed */
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2024-01-07 23:57:24 +01:00
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/*
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* Define the Event the special IRQ/INI module can handle
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*/
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#define SK_HWEV_WATIM 1 /* Timeout for WA Errata #2 XMAC */
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#define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */
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#define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */
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#define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */
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#define SK_HWEV_UPDATE_STAT 5 /* Update Statistics by PNMI */
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#define SK_HWEV_SET_LMODE 6 /* Set Link Mode by PNMI */
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#define SK_HWEV_SET_FLOWMODE 7 /* Set Flow Control Mode by PNMI */
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#define SK_HWEV_SET_ROLE 8 /* Set Master/Slave (Role) by PNMI */
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#define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
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#define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
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#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */
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#define SK_WA_INA_TIME 100000UL /* 100 msec */
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#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */
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/*
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* Define the error numbers and messages
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*/
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#define SKERR_SIRQ_E001 (SK_ERRBASE_SIRQ+0)
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#define SKERR_SIRQ_E001MSG "Unknown event"
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#define SKERR_SIRQ_E002 (SKERR_SIRQ_E001+1)
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#define SKERR_SIRQ_E002MSG "Packet timeout RX1"
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#define SKERR_SIRQ_E003 (SKERR_SIRQ_E002+1)
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#define SKERR_SIRQ_E003MSG "Packet timeout RX2"
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#define SKERR_SIRQ_E004 (SKERR_SIRQ_E003+1)
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#define SKERR_SIRQ_E004MSG "MAC 1 not correctly initialized"
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#define SKERR_SIRQ_E005 (SKERR_SIRQ_E004+1)
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#define SKERR_SIRQ_E005MSG "MAC 2 not correctly initialized"
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#define SKERR_SIRQ_E006 (SKERR_SIRQ_E005+1)
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#define SKERR_SIRQ_E006MSG "CHECK failure R1"
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#define SKERR_SIRQ_E007 (SKERR_SIRQ_E006+1)
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#define SKERR_SIRQ_E007MSG "CHECK failure R2"
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#define SKERR_SIRQ_E008 (SKERR_SIRQ_E007+1)
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#define SKERR_SIRQ_E008MSG "CHECK failure XS1"
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#define SKERR_SIRQ_E009 (SKERR_SIRQ_E008+1)
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#define SKERR_SIRQ_E009MSG "CHECK failure XA1"
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#define SKERR_SIRQ_E010 (SKERR_SIRQ_E009+1)
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#define SKERR_SIRQ_E010MSG "CHECK failure XS2"
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#define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
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#define SKERR_SIRQ_E011MSG "CHECK failure XA2"
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#define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
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#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error"
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#define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
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#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error"
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#define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
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#define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
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#define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
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#define SKERR_SIRQ_E015MSG "Parity error on RAM (write)"
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#define SKERR_SIRQ_E016 (SKERR_SIRQ_E015+1)
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#define SKERR_SIRQ_E016MSG "Parity error MAC 1"
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#define SKERR_SIRQ_E017 (SKERR_SIRQ_E016+1)
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#define SKERR_SIRQ_E017MSG "Parity error MAC 2"
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#define SKERR_SIRQ_E018 (SKERR_SIRQ_E017+1)
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#define SKERR_SIRQ_E018MSG "Parity error RX 1"
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#define SKERR_SIRQ_E019 (SKERR_SIRQ_E018+1)
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#define SKERR_SIRQ_E019MSG "Parity error RX 2"
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#define SKERR_SIRQ_E020 (SKERR_SIRQ_E019+1)
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#define SKERR_SIRQ_E020MSG "MAC transmit FIFO underrun"
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#define SKERR_SIRQ_E021 (SKERR_SIRQ_E020+1)
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#define SKERR_SIRQ_E021MSG "Spurious TWSI interrupt"
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#define SKERR_SIRQ_E022 (SKERR_SIRQ_E021+1)
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#define SKERR_SIRQ_E022MSG "Cable pair swap error"
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#define SKERR_SIRQ_E023 (SKERR_SIRQ_E022+1)
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#define SKERR_SIRQ_E023MSG "Auto-negotiation error"
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#define SKERR_SIRQ_E024 (SKERR_SIRQ_E023+1)
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#define SKERR_SIRQ_E024MSG "FIFO overflow error"
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#define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
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#define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
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#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1)
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#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error"
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#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1)
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#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected"
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#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1)
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#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)"
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#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1)
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#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)"
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#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1)
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#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)"
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#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1)
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#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)"
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#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1)
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#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1"
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#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1)
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#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1"
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#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1)
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#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2"
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#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1)
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#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2"
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#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1)
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#define SKERR_SIRQ_E036MSG "CHECK failure polling unit"
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extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
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extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
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extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
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extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
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extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
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extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
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2024-01-07 23:57:24 +01:00
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#endif /* _INC_SKGESIRQ_H_ */
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